1. Field of the Invention
The present invention relates to non-volatile memory devices, and more particularly to a non-volatile memory device and related method that use a program current clamp.
2. Description of the Prior Art
Non-volatile memory is a type of memory that retains information even when no power is supplied to memory blocks thereof. Some examples include magnetic devices, optical discs, flash memory, and other semiconductor-based memory topologies. Some forms of non-volatile memory have bits defined in fabrication, some may be programmed only once (one time programmable ROM, OTP ROM), and other types may be programmed and reprogrammed many times over. As semiconductor memory technologies are scaled down, memory cell programming and reading times have decreased (making memory cells faster), require less current/power to operate, and have improved reliability. Further, program bias voltage decreases in advanced technology.
Memory cells are typically programmed through CHEI. CHEI occurs when channel carriers traveling from source to drain of a metal-oxide-semiconductor (MOS) transistor are heated due to drain-source voltage applied across the drain and the source. The hot electrons at the end of the channel have high energy, and are injected into a floating gate of the MOS transistor approximately in a direction perpendicular to the floating gate. However, a corner effect causes multiple issues when using CHEI to program, including longer programming time, wider array distribution, higher power consumption, and poor reliability due to hole damage. To compensate for the corner effect, circuit design becomes more complex and requires larger area.
Please refer to FIG. 1, which is a diagram illustrating a memory cell 10 comprising a memory transistor 100 and a select transistor 110 according to the prior art. As shown in FIG. 1, a control line voltage ZCL is connected to the gate of the memory transistor 100, and a bit line voltage BL is connected to the drain of the memory transistor 100. Moreover, a word line voltage ZWL is connected to the gate of the select transistor 110 and a source line voltage SL is connected to the source of the select transistor 110. The source line and the n well NW are at a common voltage level (VSL=VNW).
Please refer to FIG. 2 and FIG. 3, which are a diagram illustrating gate current versus gate voltage for a fixed control line voltage ZCL, and a diagram illustrating threshold voltage and CHEI current versus time for the fixed control line voltage, respectively. At an initial programming voltage Vt_ers corresponding to the memory transistor 100 being in an erased state, gate current obtained by applying the control line voltage ZCL is higher near the initial programming voltage Vt_ers, and lower the further away the control line voltage ZCL is from the initial programming voltage Vt_ers. However, during programming, threshold voltage Vt of the memory transistor 100 may shift. Thus, when the control line voltage ZCL applied during programming is fixed, a channel hot electron injection (CHEI) current profile obtained over time approximates that shown in FIG. 3 (convolution of the two areas shown in FIG. 2). As shown in FIG. 3, CHEI current is initially high and threshold voltage Vt of the memory transistor 100 increases rapidly. However, as the threshold voltage Vt increases, the CHEI current tapers off, and increase of the threshold voltage Vt slows down. This behavior leads to slow, inefficient programming of the memory transistor 100.